With development in the semiconductor manufacturing industry, integrated circuits with better performance and more powerful functions require greater element density; besides, sizes of and spaces between the components have to be further scaled down (which has already reached the nanometer-level nowadays). Accordingly, various micro effects come up along with downscaling in sizes of semiconductor devices. In order to meet the demands in developing semiconductor devices, persons skilled in the art are dedicated to exploring new manufacturing processes.
Silicon-On-Insulator (SOI) devices exhibit good feature of dielectric isolation, thus the integrated circuits made of SOI exhibit such advantages as small parasitic capacitance, high integrated density, fast operation speed, simple manufacturing process and alleviated short-channel effect. Usually, an SOI substrate mainly consists of three layers, which are respectively a body silicon layer, a Buried Oxide layer (BOX layer) on the body silicon layer, and an SOI layer on top of the BOX layer; the material of which is usually monocrystalline silicon.
In the prior art, when contacts to the source/drain regions are formed on a semiconductor device using aforesaid SOI substrate, contact resistances are relatively large, since the contact area between bottoms of the contacts and the source/drain regions becomes limited with downscaling of the device size. However, the contact resistances should be desirably reduced in order to enhance performance of the semiconductor device. As shown in FIG. 1, an SOI substrate may be etched first, for example, an SOI layer 11 and a BOX layer 12 on both sides of a gate structure 16 may be etched to form trenches, from which the BOX layer 12 is exposed; then, a metal layer 15 is formed inside the trenches, and the metal layer 15 is in contact with the SOI layer under the gate structure 16. Because resistivity of a metal is far lower than that of a semiconductor material, thus the semiconductor structure shown in FIG. 1 exhibits lowered contact resistances. However, said semiconductor structure still has shortcomings, for example, when a semiconductor device manufactured from said semiconductor structure is in operation, a relatively large capacitance shall arise between the metal layer 15 and the body silicon layer 13, which unfavorably impairs the performance of the semiconductor device.